Semiconductor memories are used in many electronic systems to store data that may be retrieved at a later time. As the demand has increased for electronic systems to be faster, have greater data capacity, and consume less power, semiconductor memories that may be accessed faster, store more data, and use less power have been continually developed to meet the changing needs. Part of the development includes creating new specifications for controlling and accessing semiconductor memories, with the changes in the specifications from one generation to the next directed to improving performance of the memories in the electronic systems.
Semiconductor memories are generally controlled by providing the memories with commands, memory addresses, and clocks. The various commands, addresses, and clocks may be provided by a memory controller, for example. The commands may control the semiconductor memories to perform various memory operations, for example, a read operation to retrieve data from a memory, and a write operation to store data to the memory. Data may be provided between the controller and memories with known timing relative to receipt by the memory of an associated command.
With newly developed memories, the memories may be provided with system clocks that are used for timing the commands and addresses, for example, and further provided with data clocks that are used for timing of read data provided by the memory and for timing of write data provided to the memory. The memories may also provide clocks to the controller for timing provision of data provided to the controller.
The external clocks provided to the memories are used to provide internal clocks that control the timing of various internal circuits during a memory operation. The timing of the internal circuits during memory operation may be critical, and deviations in the timing of the clocks may cause erroneous operation. An example deviation in the timing of the clocks may be duty cycle distortion, that is, deviation from a 50% duty cycle.
Memories may include duty cycle adjuster circuits that can be used to adjust duty cycle of internal clocks that are generated from the external clocks. The duty cycle adjuster circuits may be set to a setting that adjusts the duty cycle of the internal clocks to improve duty cycle. However, the duty cycle adjustment provided by the duty cycle adjuster circuits may not improve duty cycle sufficiently unless the duty cycle adjuster circuits are set accurately.